To breeze through the CCNA test, you must ace many administrations and steering conventions that might be different to you. Between Tear, IGRP, EIGRP, OSPF, and exchanging, there are several subtleties you must ingest! It's anything but difficult to invest all your energy in those subjects and not give legitimate consideration to "simpler" advances, and after that out of the blue on test day you can't exactly recall the subtleties of those specific administrations.
One arrangement you must be more than acquainted with is straightforwardly associating sequential interfaces on Cisco switches. This is likewise an important aptitude to have in your home lab, since it enables you to add sections to your system arrangement.
A Cisco sequential interface is working as a DTE as a matter of course. The issue is that when you take a link and associate two switches legitimately by their sequential interfaces (with a DTE/DCE link, that is!), they're both hanging tight for the other to send them a clock rate. One of the interfaces must go about as the DCE and that interface must send the clock rate.
On the off chance that you can see the DTE/DCE link, you can guess by looking which switch has the DCE interface associated with it - the letters "DTE" or "DCE" will either be formed into the connector itself, or if it's a more seasoned link there ought to be a little bit of tape on the link that reveals to you what the interface type is. Be that as it may, imagine a scenario where you have no entrance to the link, or there are different links surrounding it and you can't perceive what type it is.
Run the direction "show controller sequential x", with x speaking to the interface number the link's associated with. There will be a considerable amount of yield from this order, yet the data you need is directly at the top:
R1#show controller sequential 1
HD unit 1, idb = 0x1DBFEC, driver structure at 0x1E35D0
cushion size 1524 HD unit 1, V.35 DTE link
I left off the 16 or so columns of data that comes after this, yet this is the data we need at the present time. In the event that R1 has the DTE link end, the other switch ought to have the DCE end:
R3#show controller sequential 1
HD unit 1, idb = 0x1C44E8, driver structure at 0x1CBAC8
cradle size 1524 HD unit 1, V.35 DCE link
We know now that R3 needs to supply a clock rate to R1. There's a trace of an issue in simply that smidgen of order yield - do you see what it is? How about we run show interface serial1 to get more data.
R3#show int s1
Serial1 is up, line convention is down
The line convention is down in light of the fact that there is no clockrate being provided by R3. In the event that there has been, we would have seen that in the yield of show controllers sequential 1.
This is straightforward enough to fix, however! We'll utilize the direction clockrate 56000 on R3's serial1 interface, and the line convention will before long come up.
1w2d: %LINEPROTO-5-UPDOWN: Line convention on Interface Serial1, switched state to up
This is a straightforward idea, however there are a couple of subtleties you should remember! For a home lab arrangement, you'll need a DTE/DCE link to make this work. On the off chance that you can't see the link connectors, run show controllers sequential x to check whether the switch has the DTE or DCE end of the link appended. On the interface with the DCE joined, utilize the clockrate order to bring the line convention up. It's simply that straightforward!
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